① Responsible for RTL level and netlist level simulation of memory chips; ② Responsible for project verification plan preparation, environment construction, use case design, script development, etc.

① At least 3 years working experience in IC Verification, major in electronic information / computer and so on ; ② Familiar with System Verilog / Verilog / SVA, functional coverage and random testing; ③ Proficient in using simulation and debugging tools, such as VCS, NCSIM, Verdi, etc; ④ Master at least one scripting language, such as Shell, Perl, Python, Tcl, Makefile, etc; ⑤ Have a good sense of team and the ability to quickly solve problems, strong initiative and sense of responsibility USB/PCIE/SATA/UFS/SD/EMMC/AMBA and VIPs work experience is preferred