Working Location: Hong Kong / China - Shenzhen

1. Master's or doctoral degree in relevant science and engineering disciplines such as electronics, computer science, physics, mathematics, etc. 2. Experience in RTL design using System Verilog. 3. Good ability in writing Python/Perl/Tcl scripts. 4. Knowledge of power optimization. 5. Knowledge of RISC-V instruction set, CPU architecture, and memory hierarchy is preferred. 6. Good knowledge of pipeline design principles. 7. Preferred to have experience with emulation technologies. 8. Proficiency in English listening, speaking, reading and writing. 9. Excellent learning ability, sense of responsibility and teamwork skills. 10. Experience in cross-region, cross-time zone and cross-language collaboration is preferred.