Working Location: Hong Kong / China - Shenzhen

1. Major in relevant science and engineering fields such as Electronics, Computer Science, Physics, Mathematics, etc.; Bachelor's degree or above, with priority given to candidates with higher academic qualifications. 2. Usually 3-5 years of work experience, while candidates with other years of work experience will also be considered. 3. Experience in using verification methods such as random stimulus, functional coverage, and assertion-based verification. 4. Proficiency in object-oriented programming using C++ / SystemVerilog. 5. Knowledge of mainstream design and verification tools (VCS or similar simulation tools, debugging tools like Debussy, GDB, etc.) and methodologies (e.g., UVM). 6. Good at conducting debugging verification and finding solutions to complex problems.